Manuraj Vanamala
Hyderabad
Summary
VLSI Engineer with knowledge in complex systems using System Verilog and UVM. Experience in Verilog, Python and UVM. Experienced in full design verification flow on ASIC. Experience in pre silicon and post silicon tests. Hardworking and passionate job seeker with strong organizational skills eager to secure entry-level position. Ready to help team achieve company goals.
Overview
1
1
year of professional experience
1
1
Certification
Work History
Design Verification Intern
Microchip Technology Inc.
Chennai, Tamilnadu
08.2023 - 09.2024
- Worked in Automotive Information Systems (AIS) Verification team.
- Worked on two audio related RTL designs which involves protocols like APB, AHB .Worked on functional coverage and code coverage of the blocks .Created c tests for chip level verification and python scripts for args files.
- Verification of OASPI Protocol.
Verification of Audio related protocols and achieved 100% functional coverage. - Built Python framework for running tests in Bringup boards.
- Analyzed results of post silicon tests on board.
- Implementation of framework including using Seggar Jlink for communication between chip and external host controller.
- Closely worked with validation team for post silicon tests on boards.
- Coordinated with other DV block owners on common components. Register layer automation scripts in python.
Design Intern
Mindgrove Technologies
06.2023 - 07.2023
- Worked in diverse team in startup which is now building Secure IoT Devices using Shakti processors.
- Implemented Secure Hashing Algorithm 3 ( Cryptographic Algorithm) in hardware using bluespec system verilog.
- Developed entire functional model of hash algorithm in python.
- Implemented branch predictor in hardware using BSV and achieved around 92% percent accuracy for model with global branch prediction.
- Collaborated with design team for successful project completion within deadlines.
- Supported website redesign efforts, resulting in improved site navigation and overall user experience
Sr. Application Engineer
Synopsys
Hyderabad, Telangana
09.2024 - Current
- Currently supporting the customers with VCS and Verdi tools.
Education
Dual Degree ( B.tech And M.tech ) - ECE (VLSI SPECIALISATION)
IIITDM Kancheepuram
Chennai, India06.2024
Skills
- System Verilog UVM
- Simulation tools: QuestaSim, Cadence
- RTL Design using Verilog
- C and scripting using Python
- AHB, AXI, APB protocols
- Micro-processor architecture
- Functional Coverage
- ASIC and FPGA design flow
- UVM methodology
- Automation scripting
- Quick Learner
- Team Collaboration
Certification
Paper publication with title "Designing of Secure Hashing Algorithm 3 (SHA-3) in Bluespec System Verilog and Python" at 2024 Second International Conference on Emerging Trends in Information Technology and Engineering (ICETITE)
SystemVerilog for Design and Verification v21.10 Exam Issued by Cadence Design Systems on July,17 2023
Crash course on Python
Issued by Google in march 2020
Timeline
Sr. Application Engineer
Synopsys
09.2024 - Current
Design Verification Intern
Microchip Technology Inc.
08.2023 - 09.2024
Design Intern
Mindgrove Technologies
06.2023 - 07.2023
Dual Degree ( B.tech And M.tech ) - ECE (VLSI SPECIALISATION)
IIITDM Kancheepuram
Paper publication with title "Designing of Secure Hashing Algorithm 3 (SHA-3) in Bluespec System Verilog and Python" at 2024 Second International Conference on Emerging Trends in Information Technology and Engineering (ICETITE)
SystemVerilog for Design and Verification v21.10 Exam Issued by Cadence Design Systems on July,17 2023
Crash course on Python
Issued by Google in march 2020
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