SAIKRISHNA PENJARLA

Design Verification Engineer skilled in ensuring the functionality, correctness, and reliability of complex digital designs. Expertise in creating and executing verification plans, developing test benches , and utilizing industry-standard verification methodologies such as UVM, System Verilog, and SV assertions. Proficient in simulation tools like Questa, with a strong understanding of digital design principles and protocols (e.g., AXI, AHB, APB). Knowledgeable in formal verification, functional verification.

Frontend ASIC DESIGN and Verification Engineer