Vijay Neerukanti
Hyderabad
Summary
Design Engineer with 2+ experience in DDR memory subsystem Knowledge, SOC integration, related quality checks and wants to use and improve skills and expertise in the right direction towards organization growth
Overview
2
2
years of professional experience
Work History
SoC Design Engineer
Intel
2022.08 - Current
- Worked on Memory subsystem for integrating Memory controller, PHY, and Interconnecting networks to work with DDR5 memories
- Worked on IP integration into SOC with automated scripts
- Good expertise of DDR5, LPDDR, GDDR protocols, MC, and basics of PHY trainings
- Worked on SRAMs, Register Files and ROMs for various IPs
- Worked on PLA for SOC that connects core and uncore IPs control registers
- Hands-on experience on static checks LINT flat and hierarchical models, CDC techniques, and relevant EDA tools
Education
M.Tech - Department of Electronic Systems Engineering
Indian Institute of Science(IISc)
Bangalore07.2022
B.Tech - Electronics And Communication Engineering
RGUKT IIIT Basar
Telangana08.2020
Skills
- Verilog / System Verilog
- Knowledge on SPI, UART, I2C, AMBA (APB/AHB/ AXI), Basics of PCIe protocols.
- Hands-on experience with various Lint and CDC tools
- Basics of STA
- Good Scripting skills in UNIX Shell/PERL/Python
- Good written and communication skills in team
Accomplishments
- Secured All India Rank 1413 in GATE 2020
- Prathibha award: Recipient of Prathibha award for achieving state first rank in SSC 2014
Declaration
All the information presented above are true and correct to the best of my knowledge.
Vijay Neerukanti
Timeline
SoC Design Engineer
Intel
2022.08 - Current
M.Tech - Department of Electronic Systems Engineering
Indian Institute of Science(IISc)
B.Tech - Electronics And Communication Engineering
RGUKT IIIT Basar
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