Samarasimha Reddy Guruvannagari

1. NR Small cell Base station Project

Role: gNodeB L2 Developer/Integration Lead.

Responsibilities:

• Implemented SPS feature in MAC/Scheduler, integrated and validated the functionality with commercial mobiles.
• Implemented PHR feature to get UE power budget to feed as input to UL power control algorithm.
• Implemented CSI-RS resource allocation in RRM and scheduling, decoding CSI feedback to get channel condition to feed as input to downlink AMC.
• Implemented Scheduling Request resource allocation in RRM and scheduling in MAC.
• Developed and integrated RACH state machine in MAC.
• Implemented search space selection of UE specific scheduling of downlink and uplink.
• Added PUCCH resource selection for UCI payload multiplexing cases.
• Developed interface layer based on FAPI, L1 specific API’s to communicate MAC with different Layer 1 options and different IPC Library API’s for ex: Astella L1, Intel Flexran IAPI, Synergy L1, IIT-Madras L1 (5G testbed).
• Currently Integrating Flexran 23.07 L1 with Sooktha L2/L3, completed Ue registration and 100 Mbps data flow in DL and 70 Mbps in UL, with Bentel RU.
• Frontend the technical support and real time bug support and L2 enhancements for customer (IIT-Madras-5G testbed project).
• Ported x86 L2-L3 onto ARM and integrated on Genevisio NPE-010 DU inline accelerator card, and executed L2-L3 on LX2160 ARM cores running at 2.2 Ghz, with Astella L1 and CIG RU, verified end to end call working, verified DL 1.4 Gbps and UL 200 mbps data rates on commercial mobile.

2. LTE Small Cell Base station Project

Role: eNodeB L2/L3 Developer/System Integrator.

Responsibilities:

• Carried out Small cell IODT in Jio labs Mumbai with Sooktha Small cell basestation, running on NXP platform BSC913X.
• Validated interworking with multiple EPC’s in Jio labs Mumbai, demonstrated DL/UL data rates and Handover’s (S1 and X2) between Sooktha base station and other Small cells available in Lab.
• Demonstrated PCI selection and ANR features in Jio labs
• Developed DPDK based fast path low latency FAPI transport for CRAN demo, with L2-L3 runinng on NXP T4240 RDB(PowerPC) and LS2085(ARM) with L1 running on BSC9131, this is demonstrated by NXP at MCW barcelona in 2015 and 2016.
• Involved in RLC enhancements through pacing for time critical sections to be completed with in 1 milli second TTI interval.
• Designed and restructure OAM handling in the eNodeB for the configuration.
• Involved in the development PMAL based fast path data processing on NXP BSC913X SOC

3. LTE Macro Base station Project

Role: L1 Developer/System Integrator.

Responsibilities:

• Developed LTE Release 13 physical layer downlink chain for x86 platfrom, implemented CRC addition, PCFICH, PSS, SSS, MIB, PDSCH, PDCCH Physical Layer processing, unit tested for bit correctness with matlab tools.
• Integrated standalone Turbo encoder and Turbo rate matcher developed by other team in the chain
• Developed pseudo random sequence generator for scrambling, Modulation mapper for all modulation schemes.
• Implemented IFFT processing chain to generate time domain signal from the populated resource grid.
• Integrated Layer1 in to DSP starcore processor SC3900 on NXP B4860 SOC, ported x86 PDCCH processing onto starcore DSP processor.
• Designed overall L1 processing flow, MAC to PHY FAPI processing, PHY to MAC FAPI generation, Integrated PDSCH to MAPLE B3 accelerator on B4860 SOC.
• Frontend real time bug support to customer on Layer1 release, client Kapsch carrier com.

4.NBIoT Standalone Smallcell Base station Poject

Role: L2/L1 Developer/System Integrator.

Responsibilities:

• Added support for control plane packet transfer between RLC and RRC for CP-IOT case.
• Developed NBIoT Release 13 physical layer downlink chain with NPSS, NSSS, PBCH, PDCCH, PDSCH on x86 platform.
• Implemented IFFT 128 point processing chain to generate time domain signal from the populated resource grid.
• Developed FAPI transport layer and API messages to communicate between MAC and PHY based on Small cell forum release 9 for NBIoT.
• Developed interface layer to configure, control and stream IQ samples to and fro from the USRP B210 and Lime SDR.
• Designed timing tick framework based on the SDR sampling rate to provide 1 milli second ticks to physical layer processing.
• Integrated UL chain developed by other team, and carried out end to end validation with TM500, up to 32 Users attach and data on DL and UL.
• With the integrated solution running on x86 machine with USRP B210 and radio unit verified compliance with multiple NBIoT devices with different chipset, ex; Ublox with QC chipset, SIMCOM with MTK chipset etc.

5.NBIoT Inband Smallcell Base station Poject

Role: L1 Developer/System Integrator.

Responsibilities:

• Added Inband support in the downlink chain to skip the LTE CRS RE’s based on the LTE cell PCI.
• Ported x86 physical layer functions to TMS320C66x DSP processor on TCI6638K2K SOC. Ported L2-L3 to ARM for TCI6638K2K SOC.
• Integrated shared memory based IPC library for FAPI transport provide by the SOC client Integrated NBIoT and LTE with inband same PCI configuration and validated with TM500 32 Users and commercial NBIoT devices, client Tejas Networks