Ramya Tiruvarangam
Technical Staff Engineer Physical Design
Hyderabad
Summary
Experienced Physical Design Engineer with a strong background in implementing physical design strategies and conducting static timing analysis. Proficient in working across multiple technology nodes, including 5nm, 7nm, 14nm, 32nm, and 45nm. Demonstrated success in managing complex blocks throughout the design process, from Netlist to GDSII, resulting in high-quality designs and consistently achieving "First Time Right Silicon."
Overview
14
14
years of professional experience
6
6
years of post-secondary education
3
3
Languages
Work History
Technical Staff Engineer Physical Design
Microchip
Hyderabad
11.2022 - Current
- Leading physical design projects, ensuring timely delivery and high-quality standards
- Designed and optimized clock tree networks to ensure minimal skew and jitter, enhancing overall timing performance and reliability of the chip.
- Improved design convergence by optimizing the foundation flow, reducing design cycle time at various stages.
- Collaborated closely with RTL and physical design teams to define and refine timing constraints, achieving 100% timing closure
- Mentored junior engineers in industry best practices, fostering a positive learning environment within the team.
Senior Lead Engineer
SmartSOC Solutions
04.2022 - 12.2022
- Leading physical design projects, ensuring timely delivery and high-quality standards
Senior Physical Design Engineer-II
Synopsys India Pvt Ltd
04.2018 - 03.2022
- Managed physical design tasks, including floorplanning, placement, and timing closure
- Collaborated with cross-functional teams to resolve design challenges
Member of Technical Staff
GlobalFoundries
01.2016 - 03.2018
- Contributed to the development of advanced semiconductor technologies
- Implemented design changes and optimizations to improve performance
VLSI Engineer
Whizchip Design Technologies at AMD
04.2015 - 01.2016
- Worked on ECO implementation and physical verification for complex designs
R & D Engineer (Chip Backend Design Professional)
IBM India Pvt Ltd
07.2011 - 03.2015
- Focused on backend design, including timing closure and physical verification
- Proactively addressed ECOs to ensure design integrity
Technical Intern in ASIC Design Center
IBM India Pvt Ltd
01.2011 - 07.2011
- Assisted in ASIC design projects, gaining hands-on experience in design tools
Education
MTech - VLSI Design and Microelectronics
International Institute of Information & Technology
Pune, India 07.2009 - 07.2011
BTech - Electronics and Communications Engineering
Kamala Institute of Technology & Science
Warangal 01.2005 - 01.2009
Skills
- SOC Encounter
- ICC2
- Synopsys Primetime
- FM (Formality & LEC)
- IBM Physical Design
- Clock tree synthesis
- Static timing analysis
- Parasitic extraction
- Placement optimization
- Timing closure techniques
- Cross-talk reduction
- Electromigration analysis
- IR drop analysis
- Routing techniques
- Floorplanning expertise
Extra-Curricular Activities
Best NCC Cadet of 8(A) Girls BN NCC Warangal. Led junior division contingent at PRE-REPUBLIC DAY Camp, Secunderabad. First prize winner in district-level science fair. District-level volleyball player.
Personal Information
- Date of Birth: 06/21/88
- Nationality: Indian
Honors And Achievements
- Achieved 'First Time Right Silicon' on Cu45 OEM ASIC.
- Winner of 'Einstein of IPAD' contest for 'BioIntelligent Health Card.'
- Published a paper on FPGA implementation of Smith-Waterman Algorithm.
- Trained at CERI Pilani on IC Fabrication.
- Hands-on experience with Mentor Graphics tools.
Timeline
Technical Staff Engineer Physical Design
Microchip
11.2022 - Current
Senior Lead Engineer
SmartSOC Solutions
04.2022 - 12.2022
Senior Physical Design Engineer-II
Synopsys India Pvt Ltd
04.2018 - 03.2022
Member of Technical Staff
GlobalFoundries
01.2016 - 03.2018
VLSI Engineer
Whizchip Design Technologies at AMD
04.2015 - 01.2016
R & D Engineer (Chip Backend Design Professional)
IBM India Pvt Ltd
07.2011 - 03.2015
Technical Intern in ASIC Design Center
IBM India Pvt Ltd
01.2011 - 07.2011
MTech - VLSI Design and Microelectronics
International Institute of Information & Technology
07.2009 - 07.2011
BTech - Electronics and Communications Engineering
Kamala Institute of Technology & Science
01.2005 - 01.2009
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