Ramadevi Kottapally
Hyderabad
Summary
Proven track record in driving project success and team coordination at Micron, leveraging exceptional communication and collaboration skills. Expert in layout design, LVS, and DRC with hands-on experience in TSMC and GPDK processes. Demonstrated ability to meet tight deadlines and deliver high-quality work for clients like Intel and Bosch, showcasing strong schematic understanding and problem-solving prowess.
Overview
7
7
years of professional experience
1
1
Certification
Work History
Sr Analog Layout Engineer
Micron
11.2023 - Current
- Achieving successful project outcomes requires maintaining accurate documentation and meeting strict deadlines.
- Working on HBM4 logic die
- Worked on DW parity checker and TSV read/write control logic.
- Routing is a major challenge to achieve in the specified area.
- Analyzing the block and placing it in a symmetrical way to meet design specifications
- Participated in formal internal design reviews of proposed products and components.
- Interacted with subject matter experts to develop training materials and tools for personnel.
Sr Analog Engineer
Cyient Ltd
08.2021 - 11.2023
- Established strong working relationships with clients through exceptional communication skills, fostering trust and collaboration.
- Developed positive working relationships with clients to effectively coordinate work activities.
- Participated in formal internal design reviews of proposed products and components.
- Provided input to the team lead regarding areas for process and procedural improvement.
- Trained and mentored junior engineers, providing guidance and direction.
- Worked on various types of modules and blocks, such as AIN_BIAS, AIN_OUTPUT, VIN_MONITOR, and SW_TOP, in TSMC 130nm BCD Process using Cadence, Virtuoso, and Calibre.
Analog Layout Engineer
Capgemini
09.2017 - 08.2021
- Developed high-quality engineering layouts and plans to meet industry standards.
- As an individual contributor, I worked on the layouts of CTLE & LDO blocks using various technologies such as TSMC 10nm and TSMC 7nm. I utilized Cadence Virtuoso and ICV as verification tools.
Education
Analog Layout Training - VLSI
Institute Of Silicon Systems
Hyderabad, India08.2017
Master of Engineering - ES&VLSI Design
Osmania University
Hyderabad, India09.2016
Bachelor of Technology - Electronics & Communication Engineering
Jawaharlal Nehru Technological University
Hyderabad, India05.2013
Skills
- Layout Design
- LVS
- DRC
- EM
- IR
- Debugging
- Cadence Virtuoso
- VLSI
- Floor Planning
- Antenna
- CMOS
Certification
- Analog Layout, Institute Of Silicon System -May 2017- Aug-2017
Languages
English
Advanced (C1)
Telugu
Bilingual or Proficient (C2)
Timeline
Sr Analog Layout Engineer
Micron
11.2023 - Current
Sr Analog Engineer
Cyient Ltd
08.2021 - 11.2023
Analog Layout Engineer
Capgemini
09.2017 - 08.2021
Analog Layout Training - VLSI
Institute Of Silicon Systems
Master of Engineering - ES&VLSI Design
Osmania University
Bachelor of Technology - Electronics & Communication Engineering
Jawaharlal Nehru Technological University
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