Rajesh Suvvari

SoC RTL Integration ( December 2020 - Present ):

• Currently working as DFT RTL integration Lead.
• Worked in RTL integration team where I implemented DFT Networks including SSN, IJTAG, JTAG and other DFT networks in complex SoC's based on floorplan using in-house DFT tools.
• Implemented Master/Child OCC to ensure scannability of testable clocks and proper synchronization between clock controllers across different partitions.
• Worked with ATPG team to resolve scannablitily issues reported in Spyglass DFT.
• Worked on ICL Extraction and retargeting Scan patterns.
• Worked with cross-functional teams for smooth DFT RTL execution.
• Performed static checks like VCLP, Lint and connectivity checks for proper RTL correctness.

ATPG Team ( September 2019 - December 2020 ):

• Worked on tasks including Pattern generation (stuckat, atspeed) and Gate level simulations (both timing and zero-delay) including debug.
• Worked with validation team to generate test sequence to enable ATPG pattern working on silicon.

DFX IP Verification ( March 2018 – September 2019 ):

• Verified JTAG, Scan networks for their correctness.
• Found several bugs on Scan architecture in RTL phase of design and ensured proper design changes were done to fix them.
• Enabled automation to check functional frequencies for atspeed clocks and test clocks.
• Was part of Silicon bring-up team to enable successful power-on of silicon.

• Handled post silicon debug pattern generation.
• Wrote ICL for ARM IP TAP and automated pattern generation which significantly improved efficiency.
• Generated FLASH IP patterns in PDL format and created complete suite of FLASH patterns in WGL format.
• Performed static CDC checks on complete design and reported many crossings with missing synchronizers.