Prasad C N J V

The Power Management Controller (PMC) Intellectual Property (IP) is integral to managing essential functions within a System on Chip (SoC), including the system boot sequence, reset protocols, sleep state management, CPU state transitions, and central power gating mechanisms. To validate the efficacy and reliability of these functions, a dedicated test bench environment has been developed, leveraging System Verilog (SV) and the Open Verification Methodology (OVM).

Contribution:

· Preparing the test plan to verify the IP.

· Enhancement for the Test bench environment.

· Writing Sequences and test cases to Verify the IP.

· Looking for Functional issues of the IPs.

· Writing cover points and analyzing the coverage.

· Integrated VCS Save/Restore feature in IP.

· Partnered with 22 team members to monitor performance, and clear the technical queries, participate in all the reviews including quality reviews and testplan reviews.

• Project Title: SOC Verification (XPROP)
• Client: Intel, Malaysia
• A chipset is a set of electronic components in an integrated circuit that manage the data flow between the processor, memory, and peripherals.
• Contribution:
• To enhance the process of identifying bugs at the System on Chip (SoC) level, it's crucial to leverage regression testing with XPROP. This approach not only streamlines the detection of anomalies but also significantly improves the accuracy and efficiency of the testing process. By integrating XPROP into our regression testing framework, we can simulate more realistic operational conditions, thereby uncovering potential issues that might not be evident under conventional testing methods. This methodical integration facilitates a more thorough examination of the SoC, ensuring a robust and reliable system performance.

• Client: Synopsys India
• Processor is a combination of control processor and digital signal processor. It consists of high performance of scalar processor derived from ARC HS processor, augmented with a vector unit for Single Instruction Multiple Data processing.
• Contribution:
• Preparing the test plan to verify the processor.
• Writing test cases to Verify the processor.
• Looking for Functional issues of the processor.
• Writing cover points and analyzing the functional coverage.

• Client: Intel Corporation.
• The Power Management Controller (PMC) Intellectual Property (IP) is integral to managing essential functions within a System on Chip (SoC), including the system boot sequence, reset protocols, sleep state management, CPU state transitions, and central power gating mechanisms. To validate the efficacy and reliability of these functions, a dedicated test bench environment has been developed, leveraging SystemVerilog (SV) and the Open Verification Methodology (OVM).
• Contribution:
• Preparing the test plan to verify PMC features like Boot Flow, Reset Flow, Global Reset, and low power modes.
• Enhancement for the Test bench environment.
• Writing Sequences and test cases to Verify PMC features.

• Client: TI India.
• A chipset comprises a collection of electronic components within an integrated circuit, tasked with overseeing the flow of data among the processor, memory, and peripherals. This critical function ensures that the system operates efficiently and cohesively.
• Contribution:
• Preparing the test plan to verify the modules Timers, WD Timers, Counter 32K and MCSPI.
• Involved in writing test cases in C and debugging.
• Furthermore, an integral part of this validation process involves the analysis of functional coverage. This analysis ensures that all aspects of the chipset's functionality are thoroughly tested, thereby guaranteeing a high level of system reliability and performance. Through a combination of strategic test planning, detailed test case development, and comprehensive functional coverage analysis, the validation team plays a pivotal role in enhancing the chipset's operational integrity.