PRAJJWAL SONI
AMS Verification Engineer-II
Hyderabad
Summary
Dynamic and enthusiastic AMS Verification Engineer with strong academic foundation in Microelectronics and Electrical and Electronics Engineering.Considerable Knowledge of Analog and Mixed Signal Verification,Hspice and Cadence Virtuoso.Adept at Verilog -A, Verilog-AMS,System Verilog, with a keen interest in breaking into Analog IC Design.
Overview
2
2
years of professional experience
10
10
years of post-secondary education
2
2
Languages
Work History
AMS Verification Engineer-II
Microchip Technology Inc.
01.2024 - Current
- Developed comprehensive test cases to validate design specifications, increasing overall product quality.
- Identified causes of equipment failures and made suggestions for issue resolution.
- My responsibilities include utilizing my skills in Cadence Virtuoso, Hspice, Primesim, and Symphony Simulator to test, circuit designs efficiently, within a given time frame.
- Developed Verilog-AMS models for various Analog Top blocks, including Bandgap references, Voltage detector, and buffers, etc.
Student
BITS Pilani, K.K Birla Goa Campus
08.2022 - 07.2024
- Designed and used a two-stage op-amp after checking its stability conditions.
- Had a successful simulation in cadence virtuoso
- Designed and simulated schematic of a two-stage OTA on the 45nm CMOS technology node.
- Achieved 63 dB DC Open Loop Gain, 55 degree Open Loop Phase Margin, and 7.8 dB Gain Margin at unity gain Bandwidth of 92 MHz.
- A precisely valued capacitor was designed using 3D NMOS in synopsys TCAD.
- Various effects of varying device dimensions on capacitance value were plotted and observed.
- Design of schmitt trigger circuit using op-amp.
Education
M.E. - Microelectronics
BITS Pilani, K.K Birla Goa Campus
Goa 04.2020 - 01.2024
B.E - B.E Electrical And Electronics Engineering
Lakshmi Narain College of Technology, Indore
Indore, India 07.2016 - 07.2020
CLASS XII -
Kendriya Vidhalaya No-2
04.2014 - 04.2015
CLASS X -
Kendriya Vidhalaya No-2
Indore 04.2012 - 04.2013
Skills
Cadence Virtuoso
Hspice
Verilog
Verilog-A
Primesim Simulator
Symphony Simulator
Unix/Linux
Solido Wave Visualiser
Analog IC design
Analog Electronics
Timeline
AMS Verification Engineer-II
Microchip Technology Inc.
01.2024 - Current
Student
BITS Pilani, K.K Birla Goa Campus
08.2022 - 07.2024
M.E. - Microelectronics
BITS Pilani, K.K Birla Goa Campus
04.2020 - 01.2024
B.E - B.E Electrical And Electronics Engineering
Lakshmi Narain College of Technology, Indore
07.2016 - 07.2020
CLASS XII -
Kendriya Vidhalaya No-2
04.2014 - 04.2015
CLASS X -
Kendriya Vidhalaya No-2
04.2012 - 04.2013
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