Overall experience as FPGA Design Engineer in RTL Design, VHDL, Verilog, Algorithm development, Image and Video Processing, Knowledge of AI/ML concepts, CNN, Python Programming, Scripting Languages like PERL, Python, TCL, Xilinx FPGA Architecture, Communication Protocols,Bus Protocols,Serial Communication Protocols, Hardware Validation, Timing Closure.
FPGA Design, RTL Coding, Validation, Debug, SDK, Vivado, Vitis, Project Planning.
FPGA Lead,FPGA Design, Work Schedule Plan, On-Site KT, Training Junior Engineers
Worked on Ultrasound machine 16 Channel transmitter board design.