Summary
Overview
Work History
Education
Skills
Certification
Timeline
Generic
MURALI YANAMANDALA

MURALI YANAMANDALA

Bengaluru

Summary

Overall experience as FPGA Design Engineer in RTL Design, VHDL, Verilog, Algorithm development, Image and Video Processing, Knowledge of AI/ML concepts, CNN, Python Programming, Scripting Languages like PERL, Python, TCL, Xilinx FPGA Architecture, Communication Protocols,Bus Protocols,Serial Communication Protocols, Hardware Validation, Timing Closure.

Overview

12
12
years of professional experience
1
1
Certification

Work History

Self Employed

Self-Employed
11.2022 - Current

FPGA Design, RTL Coding, Validation, Debug, SDK, Vivado, Vitis, Project Planning.

FPGA SW IP Dev Engineer

Intel India
07.2022 - 10.2022

FPGA Lead,FPGA Design, Work Schedule Plan, On-Site KT, Training Junior Engineers

Senior Engineer

EInfochips Pvt. Ltd.
09.2021 - 07.2022
  • Improved project efficiency by streamlining engineering processes and implementing innovative solutions.
  • Monitored employee performance to keep projects on task.
  • Delivered high-quality products by collaborating closely with sales teams to understand customer needs and translate them into viable solutions.

Member of Technical Staff

Mirafra Technologies
08.2019 - 08.2021


  • Collaborated with cross-functional teams for successful product launches, ensuring seamless integration of new features.
  • Worked with industry leaders like Samsung, ADI, Xilinx
  • Worked on technologies like 5G Phy layer, FPGA Prototyping, CNN

Senior Design Engineer

Xilinx Technologies
05.2018 - 11.2018
  • Conducted thorough design reviews to identify potential issues and propose effective solutions early in the development process.
  • Streamlined communication within the engineering team, leading to more efficient problem-solving and a reduction in project delays.
  • Worked on Display Protocol Sub Systems, Video Timing Control IP, AXI Steaming IP, Validation of Video Protocols.

R & D Engineer

Logic Fruit Technologies
05.2015 - 04.2018
  • Established strong working relationships with clients through exceptional communication skills, fostering trust and collaboration.
  • Developed positive working relationships with stakeholders to effectively coordinate work activities.
  • Achieved successful project outcomes by maintaining accurate documentation and meeting strict deadlines.
  • Worked on Image/Video Processing algorithms like Video surveillance, Noise filtering, Feature Detection, Change Detection, Panorama generation, Contrast Enhancement, Image Restoration, Morphological Operations, Implemented Hardware Design of image/Video Processing Applications, also on Tri-Speed Ethernet for applications related to network Security.

FPGA Design Engineer

Ancor Research Labs
06.2014 - 11.2014
  • Collaborated with cross-functional teams to develop highly integrated hardware solutions.
  • Worked on SDR

Project Associate

Indian Institute of Technology, Hyderabad
10.2013 - 05.2014
  • Strengthened team dynamics through regular feedback sessions, resulting in increased productivity and improved performance.
  • Streamlined data collection processes by implementing efficient tracking systems, leading to more accurate reporting and analysis capabilities.
  • Facilitated stakeholder meetings to solicit input on project goals, priorities, and expectations to ensure alignment across all parties involved.
  • Developed FPGA Design for the Ultrasound Machine transmitter for 16 Channels.
  • Implemented the 16 Channel transmitter design on Kintex-7 evaluation board(KC705)
  • Worked on AFE5809 Evaluation board, which is an ultrasound receiver board.

Project Engineer

Niranjan IndiaUltrasounds
04.2013 - 09.2013

Worked on Ultrasound machine 16 Channel transmitter board design.

Education

Master of Science - Digital Electronics And Communication Systems

Madanapalli Institute of Technology And Sciences
Madanapalli
10-2012

Bachelor of Science - Electronics And Communications Engineering

Siddharth Institute of Engineering And Technology
Puttur
05-2010

Skills

  • VHDL and Verilog proficiency
  • FPGA programming
  • Design verification
  • Scripting languages
  • Embedded systems design
  • High-level synthesis
  • Logic synthesis
  • Place and route techniques

  • Timing analysis
  • IP core integration
  • TestBench creation
  • Ethernet standards
  • JTAG debugging
  • Serial communication protocols
  • RTL design expertise

Certification

  • VLSI and Embedded Hardware Design(PG Diploma).
  • Advance FPGA Design with Xilinx FPGAs.
  • Designing with 7 Series, Ultrascale and Ultrascale+ FPGAs.
  • Embedded System Design with Zynq Socs and Vivado, Vitis.
  • Machine Learning(Coursera)
  • Image De-noising Using Auto Encoders in Python.
  • Complete Python based Image Processing and Computer Vision.

Timeline

Self Employed

Self-Employed
11.2022 - Current

FPGA SW IP Dev Engineer

Intel India
07.2022 - 10.2022

Senior Engineer

EInfochips Pvt. Ltd.
09.2021 - 07.2022

Member of Technical Staff

Mirafra Technologies
08.2019 - 08.2021

Senior Design Engineer

Xilinx Technologies
05.2018 - 11.2018

R & D Engineer

Logic Fruit Technologies
05.2015 - 04.2018

FPGA Design Engineer

Ancor Research Labs
06.2014 - 11.2014

Project Associate

Indian Institute of Technology, Hyderabad
10.2013 - 05.2014

Project Engineer

Niranjan IndiaUltrasounds
04.2013 - 09.2013

Master of Science - Digital Electronics And Communication Systems

Madanapalli Institute of Technology And Sciences

Bachelor of Science - Electronics And Communications Engineering

Siddharth Institute of Engineering And Technology
MURALI YANAMANDALA