Manuraj Vanamala
Hyderabad
Summary
VLSI Engineer with knowledge in complex systems using System Verilog and UVM. Experience in Verilog, Python and UVM. Experienced in full design verification flow on ASIC. Experience in pre silicon and post silicon tests. Hardworking and passionate job seeker with strong organizational skills eager to secure entry-level position. Ready to help team achieve company goals.
Overview
1
1
year of professional experience
1
1
Certification
Work History
Sr. Application Engineer
Synopsys
Hyderabad
09.2024 - Current
- Currently supporting the customers with VCS and Verdi tools.
- Working coverage and low power verification-related issues.
- Providing technical support for existing applications, troubleshooting problems and resolving issues in a timely manner.
Design Verification Intern
Microchip Technology Inc.
Chennai, India
08.2023 - 09.2024
- Worked in Automotive Information Systems (AIS) Verification team.
- Worked on two audio-related RTL designs, which involve protocols like APB and AHB. Worked on functional coverage and code coverage of the blocks. Created C tests for chip-level verification and Python scripts for args files.
- Verification of OASPI Protocol. Verification of Audio related protocols and achieved 100% functional coverage.
- Built Python framework for running tests on Bringup boards.
- Analyzed results of post-silicon tests on board.
- Implementation of framework, including using Segger J-Link, for communication between chip and external host controller.
- Closely worked with the validation team for post-silicon tests on boards.
- Coordinated with other DV block owners on common components. Register layer automation scripts in Python.
- Good understanding about Ethernet protocol.
Design Intern
Mindgrove Technologies
Chennai, India
06.2023 - 07.2023
- Worked in diverse team in startup which is now building Secure IoT Devices using Shakti processors.
- Implemented Secure Hashing Algorithm 3 ( Cryptographic Algorithm) in hardware using bluespec system verilog.
- Developed entire functional model of hash algorithm in python.
- Implemented branch predictor in hardware using BSV and achieved around 92% percent accuracy for model with global branch prediction.
Education
Dual Degree ( B.tech And M.tech ) - ECE (VLSI SPECIALISATION)
IIITDM Kancheepuram
Chennai, India05-2024
Skills
- SystemVerilog and UVM
- Simulation tools: Verdi,VCS,QuestaSim
- RTL design using Verilog
- C and scripting using Python
- AHB, AXI, APB protocols
- Microprocessor architecture
- Functional coverage
- ASIC and FPGA design flow
- UVM methodology
- Automation scripting
- Quick learner
- Team Collaboration
Certification
Paper publication with title "Designing of Secure Hashing Algorithm 3 (SHA-3) in Bluespec System Verilog and Python" at 2024 Second International Conference on Emerging Trends in Information Technology and Engineering (ICETITE)
SystemVerilog for Design and Verification v21.10 Exam Issued by Cadence Design Systems on July,17 2023
Crash course on Python
Issued by Google in march 2020
Affiliations
- Hotel Affairs (SAC member) in the college for year 2022-23.
- National Cadet Corps (NCC) A, B and C certificate holder .
- Represented India and lead electronics team in international competitions (SAUVC and MATE ROV) .
- Electronics lead in the SAE BAJA 2023.
- QMS lead and Hospitality lead for the annual cultural fest .
Timeline
Sr. Application Engineer
Synopsys
09.2024 - Current
Design Verification Intern
Microchip Technology Inc.
08.2023 - 09.2024
Design Intern
Mindgrove Technologies
06.2023 - 07.2023
Dual Degree ( B.tech And M.tech ) - ECE (VLSI SPECIALISATION)
IIITDM Kancheepuram
Similar Profiles
Jixiang DingJixiang Ding
Senior ASIC Verification Engineer at SynopsysSenior ASIC Verification Engineer at Synopsys
Elin IssaviElin Issavi
Sr. Event Manger at SynopsysSr. Event Manger at Synopsys
Sai Vivek PidaparthiSai Vivek Pidaparthi
Associate Network Engineer at SynopsysAssociate Network Engineer at Synopsys