kavya kotha
Logic Design Methodology Engineer
Hyderabad
Summary
At Intel Technology Pvt Ltd, I spearheaded the enhancement of design methodologies, significantly improving system efficiency through the deployment of RTL Quality Flows. My proficiency in Perl and exceptional communication skills fostered trust and collaboration across teams, establishing new standards for integration and quality in logic design.
Overview
5
5
years of professional experience
6
6
years of post-secondary education
Work History
Logic Design Methodology Engineer
Intel Technology Pvt Ltd
Hyderabad
01.2020 - Current
- Established strong working relationships with Design teams,vendor AE's through exceptional communication skills, fostering trust and collaboration.
- Provided input to team lead regarding New methodologies to overcome problems in Integration & quality.
- Defined Tools,flows and Methodologies to various projects ensuring high quality
- Deployed RTL Quality Flows- Collage,CDC.VCLP,Lint on various subsystems to implement system efficiency
- Ensured RTL Quality,Low power Implementation maintaining high system quality
Education
Master of Technology - Microelectronics
Bits Pilani
Pilani, India 07.2018 - 06.2020
B.Tech - Electronics And Communications Engineering
Keshav Memorial Institute of Technology
Hyderabad, India 08.2012 - 05.2016
Skills
RTL Design
Verilog Coding
Static Checks(CDC,Lint,VCLP)
Perl
RCA
EDA
Debugging
Shell script
Front End TFM
Design TR
Timeline
Logic Design Methodology Engineer
Intel Technology Pvt Ltd
01.2020 - Current
Master of Technology - Microelectronics
Bits Pilani
07.2018 - 06.2020
B.Tech - Electronics And Communications Engineering
Keshav Memorial Institute of Technology
08.2012 - 05.2016
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