Summary
Overview
Work History
Education
Skills
Certification
Timeline
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CHENCHU KISHORE YENDODU

Hyderabad

Summary

  • Passionate Physical Design Engineer having 8+ years of experience in Chip Designing and has strong knowledge of the complete IC design cycle.
  • Strong fundamentals in physical design execution through handling diverse blocks in multiple projects from 22nm- 90nm technology.
  • Expertise in Designing and Implementation of Low Power Techniques in IC Design, Having full knowledge of Unified Power Format (UPF), CPF and Low power Implementation techniques to achieve lower consumption with better IC performance.
  • Vastly works in IoT Domain with Designs having a lot of power domains ~150 and successfully achieved Industry the best Power Metrics.
  • Certified as Low Power Implementation Designer in IoT ASIC's.
  • Having Strong knowledge in Floorplanning, Macros placement, Power Planning and Physical Implementation with both Synopsys (Fusion Compiler, ICC2 Compiler) and Cadence (Encounter and Innovus) EDA tool sets.
  • Expertise in Physical Implementation includes PnR, Clock Tree Synthesis(CTS), RC - Extraction with both Synopsys and Cadence tool sets
  • Having Strong knowledge in timing closure with both Synopsys (Prime Time) and Cadence (Tempus) tool sets.
  • Implemented lot of ECO's which are related to Timing and Design Rule Fixing.
  • Having strong knowledge in Design Planning and Library Preparations includes Memory Generation from different Vendors, Constraint Development of blocks with various clocks.
  • Strong knowledge in Front End Implementation of IC Design with both Synopsys (Fusion, Design Compiler) and Cadence (Genus) tools.
  • Having Strong knowledge in various Front End Implementation checks includes Lint Checking, Clock Domain Crossings, Formal Verification and Low power checks with both Synopsys (Formality, VSI-LP) and Cadence (Conformal LEC and Conformal LP) tool sets.
  • Strong knowledge in Implementation of different DFT modes (MBIST and SCAN) in the Design.
  • Strong knowledge in device physics and research experience which focused on the design, Integration and Implementation of novel, digital on-chip voltage sensing schemes in nanometer CMOS.
  • Strong knowledge in Physical Verification includes Design Rule Check(DRC), Layout vs Schematics (LVS), SignalEM, Electro Static Discharge(ESD), Electrical Rule Check (ERC) and power ramp-up analysis with Calibre tools.
  • Expertise in execution and debugging Low Power issues like Dynamic/Static IR Drop and Power Network Improvements based on the IR Drop results with both Apache and Voltus Tools.
  • Expertise in Scripting languages like Perl, TCL.
  • Expertise in IoT Design Architecture with different Power Scenarios and clocks.
  • Successfully Implemented lot of Low Power (Clock Gating, Power Gating and Dynamic Voltage Scaling) techniques to achieve best power metrics.
  • Certified in VLSI Physical Design and Embedded Systems in 2016
  • Having strong knowledge in Verilog, System Veriog Coding and having basic knowledge of UVM.
  • Having Strong knowledge in different WIFI Protocols includes 802.11b, g, n, ah and ax, Having basic knowledge on Bluetooth protocol.
  • Having Strong knowledge in C, C++, Data Structures and LINUX Programming.
  • Expertise in Firmware Development, Strong knowledge on RTOS Concepts.
  • Strong knowledge from Application to Hardware Communication.
  • EDA Tools : Genus, Conformal LEC, Conformal LP, Encounter, Innovus, Tempus, Voltus, Calibre, Apache, Design Compiler, Test Compiler, Formality, VSI-LP, Fusion Compiler, ICC2 and Prime Time.

Overview

8
8
years of professional experience
1
1
Certification

Work History

Associate Staff Physical Design Engineer

Silicon Labs
01.2023 - Current
  • Ongoing Project : Physical Implementation of Wireless IC in 40nm (Lion)
  • Role : PG Lead
  • This IC is a derivative product from our past series of products.
  • This is a customer specific product which enhances the Flash and Internal SRAM size and with more security features added.
  • Completed the UPF changes, Front End Implementation which includes the frontend checks (LEC, CLP) and released the netlist.
  • Completed Floorplan analysis, Physical cells placement and power grid Implementation and PnR is in progress.
  • Supporting 2 packages QFN40 and WLCSP, Completed analysis of both and released package gds to the team.
  • Remaining things were on going.
  • Recently Completed Project : Physical Implementation Wireless IC in 22nm (Rainier)
  • Role : PnR Lead
  • This IC we are developing in 22nm technology having MCU, Security and Low Power Wireless (Bluetooth, Zigbee and Z-Wave etc..) Subsystems.
  • Successfully completed design planning, Library Creation with 22nm PDK's, Memory Generations with the latest compilers and validated.
  • Successfully completed Low Power Implementation requirements like Power Grid Analysis for proper power planning, UPF, SDC Creation etc..
  • Responsible for completing the Implementation of one block (Low Power Wireless) from Physical Synthesis to Signoff.
  • Completed Front End Implementation, Formality and Low power checks.
  • Created Floorplan, Power Grid Analysis with Voltus tool, Power Planning and pre wiring (Analog to Digital blocks connections) is done with multiple analysis.
  • Successfully completed the package analysis for QFN40 and QFN32 package and did bonding and released the GDS to the packaging team.
  • Completed Physical placement, CTS and Routing by using Cadence Innovus Implementation tool.
  • Successfully resolved all DRC's seen in the Calibre, Worked on the LVS, ERC, Float checks and resolved all issues and made it clean.
  • Worked on the Current Density, P2P, Latchup and Topology checks and made the database clean.
  • This IC we are Implementing in a Flat Implementation approach.
  • Experiments with Synopsys Fusion Compiler for better PPA (Power, Performance and Area) are done.
  • EDA Tools using in this Project : Genus, Innovus, Conformal CLP, Conformal LEC, Tempus, Voltus, Calibre, Virtuoso.
  • Gate Count : ~4M

Lead Physical Design Engineer

Silicon Labs
04.2021 - 12.2022
  • Project : Physical Implementation of Wireless IC in 40nm (Si9117 revB0)
  • Role : PnR Lead
  • This project was done in 40nm process node and I've involved starting from design phase to GDS Delivery to Foundry.
  • It is a Single Band (2.4Ghz) IoT IC and targeted for the Low Power and High Performance Market.
  • We have around 150 Power domains and Maximum clock frequency is 200Mhz.
  • This Design is having 5 Subsystems, and I've completed Front End and Back End Implementation for each subsystem and finally CHIP, with Hierarchical Implementation Flows.
  • Successfully completed Design Planning, Library preparations, UPF Creation, SDC Development, Memory Generations.
  • Successfully completed Front End Implementation which involves Lint Checking, CDC Analysis, Physical Synthesis.
  • Debugged and resolved lot of design issues during formal verification, Low power checks and Timing Analysis.
  • Successfully Completed Floorplan, Power Planning, Placement, Clock Tree Synthesis (CTS), Routing with targeted PPA.
  • Vastly worked in Physical Verification which includes DRC, LVS, ERC, SignalEM and ESD and closed successfully.
  • Performed a lot of iterations with power network to achieve best IR Drop results and successfully achieved.
  • EDA Tools used in this project : Design Compiler, Formality, VSI-LP, Innovus, Prime Time, Quantus, Calibre.
  • Gate Count : ~5M

Senior Physical Design Engineer

Silicon Labs
04.2018 - 03.2020
  • Project : Physical Implementation of Wireless IC in 40nm (RS9117)
  • Role : PnR Engineer
  • This Project was done in 40nm process node, and I've involved mainly in the Back End Implementation and Physical Verification.
  • It is a Single Band(2.4Ghz) IoT IC and targeted for the Lower power for Home BU Applications.
  • Successfully completed Power Architecture for this IC and having around 130 Power Domains and Maximum Clock Frequency is 180Mhz.
  • PnR Execution for all 5 subsystems we have in our IC from netlist to GDS and coming up with recipes and methodologies for power, performance and area.
  • Successfully completed Floorplanning, Power Grid Analysis, Power Planning, Placement, Clock and Power distribution timing closure.
  • Responsible for working with logic design team to understand various partition architectures and drive physical aspects early in the design cycle to meet the schedules and design goals.
  • Developed a lot of automation flows and scripts for smoother execution and faster turnaround.
  • Completed Timing Analysis and closure for 2 out of 5 subsystems and all other digital blocks in Analog.
  • Done a lot of analysis on IR DROP and Implemented an automated script to place the Decaps, Well Taps and Power Switches in the Design to achieve lower power numbers with Max possible performance.
  • Successfully completed Physical Verification of this IC which includes DRC, LVS, ERC and ESD with the calibre tool.
  • EDA Tools used in this project : Design Compiler, Formality, VSI-LP, Innovus, Prime Time, Quantus, Calibre.
  • Gate Count : ~4.5M

Physical Design Engineer

Redpine Signals
02.2016 - 03.2018
  • Project : Physical Implementation of Wireless IC in 40nm (RS9116)
  • Role : PnR Engineer
  • Responsible for Front End Implementation of all 5 subsystems are there in this IC and completed them successfully with all front end checks includes Lint, CDC, Formal Verification, Low Power Verification and Timing analysis.
  • Responsible for Back End Implementation of 1 subsystem and successfully delivered this as an IP.
  • Successfully completed Physical Implementation of 1 block from Netlist to Signoff includes Floorplanning, Power Planning, Placement, CTS, Routing with Cadence tool sets.
  • Completed Physical Verification for this Block successfully.
  • Developed flows and scripts for Power planning and automatic floorplan for faster execution without manual effort.
  • Developed several scripts for reducing shorts and congestions issues in the design.
  • Expertised in the Unified Power Format(UPF) and Constraints Development and successfully developed for this block.
  • I've Involved in one IC(External RF IC) developement which was in 90nm and understood 90nm PDK's, Design Rules and in actual Implementation of this IC.
  • Expertised in different SCAN techniques in the Flow(stuckAT and AT-Speed) and closed Timing for these Test modes.
  • Involved in Physical Verification of this IC and got exposure on different techniques to resolve various DRC's.
  • EDA Tools used in this Project : VCS, Design Compiler, Formality, VSI-LP, Innovus, Prime Time, Quantus, Calibre.
  • Gate Count : ~1.5M

Software Engineer

Redpine Signals
02.2016 - 03.2018
  • Project : Software Developement for WIFI Standards (802.11a/b/g/n and ah)
  • Role : Software Developer
  • Developed a Firmware for 802.11n Wireless Standard and successfully validated with RS9113 Module.
  • Successfully Developed an Integrated Firmware which is the solution for Marvell 11AC (5Ghz) and our RS9113 (2,4Ghz) module
  • I have successfully integrated Marvell Free RTOS Based firmware to our Firmware and created a workable solution for Dual Band module.
  • Successfully developed Firmware for 802.11ah Wireless standard and validated successfully with Qualcomm's AP.
  • Successfully developed Linux USB and SDIO Device Driver for RS9113 Module.
  • Expertised in Device Drivers programming and developed MAC80211 Based driver in the Linux OS.
  • Developed a Firmware (Which was there in Assembly Language) to meet the timing requirements with the hardware(it is not able to meet the SIFS (ACK Response Time) If we Implement this code with High level language).
  • Developed a lot of Application Softwares for various product requests from customers.
  • Successfully developed a firmware for 802.11a Wireless Standard and successfully validated with External RF Module which was developed in 90nm process node.
  • Successfully developed a firmware for 802.11P wireless standard(5.9Ghz) and verified with third party 802.11p supported modules.
  • Developed a lot of firmwares to validate the Modules during manufacturing phase (ATE).
  • Expertised in full stack development starting from Application, Driver, Kernel, Firmware.
  • Expertised in Real Time Operating systems, JTAG, Kernel Programming and lot of software techniques.

Education

Masters in MicroElectronics -

Birla Institute of Technology, Pilani

Bachelors Degree in Electronics -

Jawaharlal Nehru University

Skills

  • ASIC Physical Design
  • RTL Design
  • Synthesis
  • Floorplanning
  • Place and Route
  • STA
  • Physical Verification
  • Verilog
  • System Verilog
  • TCL
  • Perl
  • C
  • C
  • WI-FI
  • Linux Programming
  • Device Drivers
  • Assembly Language Programming

Certification

VLSI Physical Design and Embedded Systems, 2016

Timeline

Associate Staff Physical Design Engineer

Silicon Labs
01.2023 - Current

Lead Physical Design Engineer

Silicon Labs
04.2021 - 12.2022

Senior Physical Design Engineer

Silicon Labs
04.2018 - 03.2020

Physical Design Engineer

Redpine Signals
02.2016 - 03.2018

Software Engineer

Redpine Signals
02.2016 - 03.2018

Masters in MicroElectronics -

Birla Institute of Technology, Pilani

Bachelors Degree in Electronics -

Jawaharlal Nehru University

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